1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of controlling stepper process parameters based upon the optical properties of incoming anti-reflecting coating layers, and a system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting substrate or wafer 11 comprised of doped-silicon. The substrate 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown).
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor 10 depicted in FIG. 1, are formed above a semiconducting substrate. In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, metals, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes, along with various ion implant and heating processes, are continued until such time as the integrated circuit device is complete. Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modern semiconductor processing that features be formed as accurately as possible due to the reduced size of those features in such modern devices. For example, gate electrodes may now be patterned to a width 12 that is approximately 0.18 μm (1800 Å), and further reductions are planned in the future. The width 12 of the gate electrode 14 corresponds approximately to the channel length 13 of the transistor 10 when it is operational. Of course, the critical dimension 12 of the gate electrode 14 is but one example of a feature that must be formed very accurately in modern semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc. Thus, even slight variations in the actual dimension of the feature as fabricated may adversely affect device performance. Thus, there is a great desire for a method that may be used to accurately, reliably and repeatedly form features to their desired critical dimension, e.g., to form the gate electrode 14 to its desired critical dimension 12.
Photolithography is a process typically employed in semiconductor manufacturing. Photolithography generally involves forming a patterned layer of photoresist above one or more layers of material that are desired to be patterned and using the patterned photoresist layer as a mask in subsequent etching processes. In general, in photolithography operations, the pattern desired to be formed in the underlying layer or layers of material is initially formed on a reticle. Thereafter, using an appropriate stepper tool and known photolithographic techniques, the image on the reticle is transferred to the layer of photoresist. Then, the layer of photoresist is developed so as to leave in place a patterned layer of photoresist substantially corresponding to the pattern on the reticle. This patterned layer of photoresist is then used as a mask in subsequent etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features, that are to be replicated in an underlying process layer. The features in the patterned layer of photoresist also have a critical dimension, sometimes referred to as a develop inspect critical dimension (DICD).
Due to steadily decreasing feature sizes in semiconductor devices, it is essential not only to steadily reduce the wavelength of the light sources used in stepper tools, but also to optimize the process of energy deposition in the photoresist layer. Such optimization is required because even minor deviations from the desired pattern in the photoresist masking layer may result in irregularities of the final features, which, in turn, may reduce the reliability of the final device or even cause a total failure. One source of such undesired and uncontrollable energy deposition in the photoresist resides in the reflectivity of the underlying material layer(s) to be patterned. In particular, if one of the underlying material layers that is desired to be patterned is comprised of a metal, such as aluminum, the reflectivity of this metal layer may exceed a value of approximately 90%. Since the light reflected from the underlying layer(s) will expose resist portions that are intended to remain unexposed, resulting in an undesired broadening of features, it is desirable to suppress reflection of an underlying layer as much as possible. To this end, anti-reflective coatings (ARCs) are typically used in the photolithography process for patterning features of critical dimensions.
An ARC layer formed on top of a process layer that is to be patterned is typically designed so as to reduce the amount of light that is reflected back into the photoresist from the underlying process layer. For this purpose, three optical parameters, namely refractive index “n,” extinction coefficient “k” and thickness “d” of the ARC layer, have to be properly selected such that an appropriate phase shift is created between the light reflected at the interface between the ARC layer and the underlying process layer, and the light reflected at the interface between the ARC layer and the photoresist masking layer. If the above-mentioned three parameters “n,” “k,” “d” are properly adjusted to the wavelength of the light source used in the stepper tool, the reflectivity of underlying layers can be drastically reduced.
FIG. 2 depicts an illustrative embodiment of a wafer 11 that may be subjected to an exposure process in a stepper tool. As shown in FIG. 2, a plurality of die 42 are formed above the wafer 11. The die 42 define the area of the wafer 11 where production integrated circuit devices, e.g., microprocessors, ASICs, memory devices, will be formed. The size, shape and number of die 42 per wafer 11 depend upon the type of device under construction. For example, several hundred die 42 may be formed above an 8-inch diameter wafer 11. The wafer 11 may also have an alignment notch 17 that is used to provide relatively rough alignment of the wafer 11 prior to performing certain processes, e.g., an exposure process in a stepper tool.
The exposure process performed on the wafer 11 is typically performed on a flash-by-flash basis as the wafer 11 is moved, or stepped, relative to the light source 47. During each step, the light source (not shown) in the stepper projects light onto a given area of the wafer 11, i.e., each flash is projected onto an exposure field 41. The size of the exposure field 41, as well as the number of die 42 within each exposure field 41, may vary greatly. For example, an illustrative exposure field 41 is depicted in FIG. 2 wherein four of the die 42 fall within the exposure field 41, i.e., a so-called 2×2 pattern. However, the number of die 42 and size of the exposure field 41 may vary. For example, integrated circuits may be exposed using a 1×2 pattern (covering 2 die), a 5×5 pattern (covering 25 die), etc. The precise pattern of the exposure field 41 may be based upon the product under construction as well as the desires and judgment of the appropriate process engineer.
The optical characteristics of the ARC layer are very important if the exposure process is to result in a photoresist masking layer having the desired DICD dimensions. For example, optical characteristics such as the index of refraction (“n”) and the dielectric constant (“k”) of the ARC layer at a particular exposure wavelength, e.g., 248 nm, may impact the ability of the stepper process to produce accordingly-sized features in the layer of photoresist. More particularly, variations in these optical characteristics can cause control problems in modern manufacturing operations with its inherently low tolerance for process variations due to the very small absolute size of the features to be formed. The optical characteristics of the ARC layer may vary from wafer-to-wafer and/or from lot-to-lot due to a variety of reasons. For example, thickness variations in the ARC layer from wafer-to-wafer and/or lot-to-lot will cause the optical characteristics of these ARC layers to vary. Additionally, there may be variations in the processes, typically deposition processes, used to form the ARC layer, e.g., variations in process gases, temperature, cleanliness, film stoichiometry, etc., all of which may cause variations in the optical characteristics of the resulting ARC layers.
The variations of the optical characteristics of an ARC layer may tend to cause the DICD of features formed in the patterned layer of photoresist to be less or greater than desired. In turn, this may lead to excessive rework of the patterned layer of photoresist, i.e., the incorrectly formed layer of photoresist may have to be removed, and the process may have to be repeated. Even worse, if undetected, the variations in the patterned layer of photoresist resist resulting from the variations in the optical properties of the ARC layer, may ultimately lead to the formation of features, e.g., gate electrodes, having dimensions that are not acceptable for the particular integrated circuit device under construction. For example, transistors may be produced with gate electrodes that are too wide (relative to a pre-established target value), thereby producing transistor devices that operate at less than desirable switching speeds. All of these problems result in delays, waste, excessive costs and cause reduced yields of the manufacturing operations.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.